1. Field of the Invention
The present invention relates to a clock transferring apparatus. More particularly, the present invention relates to a clock transferring apparatus that outputs input data given in synchronization with a transmission clock in synchronization with an internal clock having a phase different from that of the transmission clock.
2. Description of Related Art
A test apparatus such as a semiconductor testing apparatus supplies a test pattern to a device under test such as a semiconductor, receives an output signal output from the device under test based on the test pattern, and judges the good or bad of the device under test by comparing the received output signal and an expected value. The output signal output from the device under test includes the variation of a delay amount caused by power supply variation and temperature fluctuation, the manufacture variation of an LSI, a substrate, and a cable. Therefore, the test apparatus receives the output signal output from the device under test by means of an internal clock of the test apparatus that has a small noise. Moreover, since the device under test operates by a clock different from the internal clock of the test apparatus, it is necessary to perform initialization synchronizing a phase of a clock of the device under test with a phase of the internal clock of the test apparatus when receiving the output signal from the device under test. Conventionally, there have been performed delivery and receipt of signals between clocks having phases different from each other by optimizing an arrangement of parts and electric wiring or by using an interleave circuit or a variable delay circuit.
Now, since a related patent document is not recognized, the description is omitted.
However, with speedup of an operation clock of a recent semiconductor device or the like, since a tolerance of setup hold time when delivering and receiving data decreases, it is difficult to guarantee to transfer from a clock to another clock by means of only an arrangement of parts and electric wiring. Moreover, when transferring from a clock to another clock using an interleave circuit, since it is necessary to provide the interleave circuit in all signal lines, the magnitude of circuit increases and also power consumption increases. Furthermore, when transferring from a clock to another clock using a variable delay circuit, since the variable delay circuit has to be provided in all signal lines and a delay amount has to be set in all variable delay circuits, initialization has required time.